Introduction of Error Correcting Schemes in the Design Process
نویسندگان
چکیده
On the road of smaller nanoscale devices perspectives, new proposals of alternatives to CMOS technology are emerging for nanoscale fabrics. This paper relies on a specific 2Dgrid nanowire fabric and proposes new CAD tool to help the designer in its nanoscale implementation, from highlevel specification to abstract layout. This tool proposes to incorporate some fault-tolerant techniques at different levels of the design process (functional level and structural level). The layout of the defect-tolerant circuit can be produced in a semi-automatic way based on the faulttolerance directives given to the tool.
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